Over the course of this article, we’ll go through most variations of the protocol used by QSPI NOR Flash devices. And as is usual with our articles, this series puts special emphasis on the impact of device features and characteristics on the software and application design. This series isn’t meant to be an introduction to NOR flash technology but is more about what differentiates one QSPI NOR flash device from another. In previous articles, we looked at the hardware characteristics of QSPI NOR devices and the internal memory organization of the flash memory. And to make things even more complicated, QSPI controllers often do not support all the variations.īut fear not, in this third entry on the ins and outs of QSPI NOR Flash devices, we look at the Quad Serial Peripheral Interface protocol and its variations in depth.
As is the form for storage devices, not all variations are supported by every device family. Including the obligatory single, dual and quad data lane modes there are over a dozen variations of the base protocol. In practice, however, the answer isn’t as simple. Extend the common SPI protocol to use 4 data lanes, thus increasing the overall bandwidth. The concept of the Quad Serial Peripheral Interface, i.e.
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